System

Compilation

The Compiler is a feature of Tesira software that analyses and validates the layout, calculates I/O and DSP processing requirements and makes an initial determination of the number and type of Tesira hardware needed. It attempts to find the minimum hardware and the lowest priced solution that would still realize the design. It also attempts to minimize the number of DSP cards and network connections. Additionally, a Compile will provide indication of system design errors via a compilation report in the Output Window. Finally, a Compile will perform automatic Delay Equalization on all audio paths, according to the Delay Equalization settings found under the General Settings section of the Document Settings control dialog window, which is accessed via Options in the File menu. 

  

  

Compile

Compiles the DSP layout for the active partition in the overall system without regard to other partitions. In the compilation process the blocks are analyzed, checked against the system hardware (systems specified in the equipment table) and formatted to be sent to that hardware. The analysis and any logical errors in the system blocks are displayed in the output window. 

  

  

Compile All

Compiles the DSP layout for all partitions in the entire system layout.  In the compilation process the blocks are analyzed, checked against the system hardware (systems specified in the equipment table) and formatted to be sent to that hardware. The analysis and any logical errors in the system blocks are displayed in the output window.  

The Compile All Uncompiled Partitions button is enabled regardless of the status of Delay Equalization.

  

  

Recompile All

Recompiles the DSP layout for all partitions in the entire system layout even if there have been no changes.

  

  

Optimize

Compiles all uncompiled partitions and analyzes the compilation results to find an equivalent, lower cost equipment allocation, if one exists. By default, the compiler finds an optimum equipment list for each partition in the system individually, and the accumulated result of this may not be cost optimal across the entire configuration, particularly in systems having a large number of partitions. Optimization may add or remove hardware from the Equipment Table if the list is functionally equivalent and lower cost. Devices in the Equipment Table with serial numbers assigned (physical devices) are not subject to removal by the optimization. Likewise, devices having DSP objects with fixed allocation will not be removed. If Optimization finds an improvement, the equipment table will be updated, and the entire layout will be recompiled. If no improvement is found, the previous compilation results are kept.

  

  

Order

Tesira software compiles each partition individually. Order manually sets the order in which partitions will be compiled. By default the partitions are compiled in the order in which they were created.

Occasionally, compiling partitions in numerical order can lead to undesired results or a compilation failure. For instance, the compiler might fully allocate I/O blocks to a unit in partition one so that there is no room for more I/O blocks in that unit. If subsequent partitions have I/O blocks that are fixed in the same unit, the compilation may fail. 

For this reason, Tesira software allows to change the compilation order of partitions. This allows partitions to be compiled in a desired order, and may help to resolve issues like the one described above. It can also be helpful to compile partitions which have large mixer blocks before other partitions, to prevent splitting of large mixer blocks over several DSP cards. 

A compilation summary can be viewed in the Output Window. 

  

  

Delay

Delay Equalization provides a way to group signal paths that are sensitive to small offsets in delay. System latencies through the system will be equalized for all paths within a defined group. See the Delay Equalization section of Document Settings for information on Delay EQ modes. 

Most audio and video input and output blocks are assigned to a Delay Equalization Group. Each I/O block’s Delay Equalization Group can be found in its Properties. 

 

Add: User defined Delay Equalization Groups may also be created by entering a group name and selecting Add. 

Delete: User defined Groups may be deleted. 

The following default groups are always available: 

• None: If required any block can be unassigned from a default or user-defined group. (meaning it will be excluded from delay equalization calculations.) 
• Default: Each audio I/O block (excludes AEC Blocks) is initially assigned to the Default group 
• Default AEC: Each audio AEC block is initially assigned to the Default AEC group 
• Default Video: Each Video block is initially assigned to the Default Video group 

Signals originating from input blocks that are in the same group will be synchronized up until the point they encounter a block with multiple inputs (e.g., mixers, routers, duckers, room combiners). Signals which feed output blocks that are in the same group are assumed to feed the same acoustic space, and will be synchronized from when they output a mixer/router block until they reach the output blocks. 

Assigning an input block to the same group as an output block is allowed, but internally they will be treated as different groups. Input signals are only synchronized with other input signals, and output signals are only synchronized with other output signals. 

  

  

Setup

Media Networks are the AVB, Dante or CobraNet connections that are being used in your Tesira configuration file.

Three Media networks are created by default and cannot be deleted. Additional media networks can be added and defined if required.

The available Media Networks are listed. Dedicated media blocks such as the AVB Input, AVB Output, Dante Input, Dante Output, Audio-Technica Mic, Shure Mic, CobraNet Input and the CobraNet Output have a drop down that is used to select the required Media Network.

A single Clock Leader (Master) can be defined in the system. This setting will define which network will be tasked with Backplane timing and synchronizing the audio across different media networks. When a Dante block is added to a layout for the first time, a Media Clock Change prompt will recommend Dante Default media network to Clock Leader. See the Clocks section of Dante Considerations for additional details about clock settings. See the Media Networks section of Application settings for details on Dante Default settings. 

Un-checking the Detect Clock Sync Faults suppresses the "clocks not synchronized on the media network" error message. An example of when a user may want to deselect this option is if two separate Tesira systems are connected and synchronized to the same Dante network, and each system has Dante selected as the Clock Leader. If these systems were then connected to the same CobraNet network, both systems would attempt to be the CobraNet conductor. In this scenario, only one system may be the conductor, so the other system would give the "clocks not synchronized on CobraNet network" error message. A system designer may suppress the error message by deselecting the "Detect Clock Sync Faults" check box for the CobraNet network. 

 

Add: Creates a default user-defined Network Name, with a format of  "UserNetwork_1", "UserNetwork_2", etc. with a default type of AVB. Once created, this can be renamed and the Network Type changed to Dante or CobraNet if needed.

Remove: Will remove a selected user-defined network. Not available on any of the three default network names.

OK: Saves any current settings and closes the window.

Cancel: Discards any current changes and closes the window.

  

  

Diagram

The Media Networks Diagram will be available after a valid Compilation has been performed. Selecting Diagram will prompt the user to perform a Compile if needed.

The dialog will show the network topology being used by all media cards in the system.

Dedicated media blocks such as the AVB Input, AVB Output, Dante Input, Dante Output, Audio-Technica Mic, Shure Mic, CobraNet Input and the CobraNet Output have a drop down that is used to select the required Media Network.

  

Media Network Info and Warnings

The Media Networks Diagram has some indicators that can be reviewed for more information. 

X Icon: Warning that there is an issue in the configuration or operation of the Media Network. 

i Icon: User Information regarding some topology or network requirements for the Associate Media network. 

  

Error Messages

AVB Control Required

There are expanders on the default AVB network. These expanders must be able to exchange control signals with their proxy servers. This requires exactly one of the following two network configurations. Either:

1. The default AVB network ports and control network ports must be plugged into the same network. Or:

2. If the default AVB network ports and control network ports are plugged into different networks, the default AVB interfaces on servers that proxy expanders must be enabled for control signaling via the network settings in device maintenance. This should not be done if these ports are plugged into the same network.

Disjoint Networks Present

All Tesira devices on media networks must have access to the system’s leader clock via one of their media network ports. This requires that there is some path from every device to the designated clock leader network. Such a path may pass through other devices in the Tesira system. In the current layout there are devices on media networks with no path to the clock leader network. These devices are indicated in red on the media networks diagram.

This error occurs when the compiler is unable to find a solution with full media-network inter-connectivity, leading to isolated media-network “islands” in the topology. To correct this problem, try to remove constraints (such as fixed allocations, etc.) that prevent the compiler from finding a connected solution. Alternately, you may add fixed-allocated blocks that force a media network connection between the isolated “islands.”

Clock Leader Unused

None of the devices in this system have media network interfaces on the designated clock leader network. Therefore the system cannot use this network as its clock leader. Either choose a different clock leader network in the media networks setup form, or else add blocks that utilize the designated clock leader.